The present invention relates to the MOS semiconductor art. Specifically, a semiconductor device having an electrically controllable channel width is described which may be used in applications where matching the electrical parameters of devices on a single integrated circuit is desirable.
Integrated circuits having MOS derived components have manufacturing tolerances which vary with position on the device, and transistors located on one portion of a semiconductor substrate may have different gain characteristics than those in other locations on the substrate. Variations in the device characteristics across the integrated circuit result from random and systematic variations in manufacturing processes. The process variations include photolithographic image size variations, etch image size variations, ion implant dopant level variations and the thickness of deposited or grown films. These variations become increasingly significant as the area of the devices decreases.
Some electronic circuit applications require that the transistors have an essentially matched gain. One such application is a digital to analog converter, wherein a ladder network is provided generating a plurality of reference currents from a constant reference current distributed throughout the integrated circuit. A designer will provide for a single source of current as the reference value, and the value of the reference current is reproduced in locations throughout the integrated circuit. Variations in transistor gain across the integrated circuit will result in random and systematic variations in reference currents which are replicated throughout the device.
The present invention has been derived to provide semiconductor devices, such as a transistor or a resistor, having electrical properties which can be matched to other similar devices located on the substrate.
The present invention provides for a semiconductor device having an electrically modulated conduction channel. The device is located within a trench structure formed in a substrate of an MOS integrated circuit, and a diffusion region within the trench structure is electrically modulated by applying a voltage between the trench and substrate.
In accordance with one embodiment of the invention, the device located within the trench structure may be an FET transistor, having a gate deposited over the diffusion region. The channel width below the gate can therefore be modulated by applying an electrical potential between the trench structure and the substrate, producing a change in the transistor gain. Accordingly, the gain of the device may be effectively set by varying the voltage potential between the trench structure and the substrate to match the gain of other transistors on the substrate.
In accordance with the invention, a pair of transistors having similar characteristics may be formed within the trench. If a known gain is established in one of the transistors, by controlling the trench to substrate potential, so that a known current flows therethrough, the gain on the other transistor is commonly controlled by the same potential between the trench and substrate, and the other transistor can be used to generate a reference current. Different pairs of transistors located in other trenches on the substrate may be set to the same gain, if the known current is set in one of the transistors. The remaining transistor of each pair of transistors in a trench may be advantageously used to generate the same reference current if their gate connections are commonly connected.
In yet another embodiment of the invention, the trench structure may include multiple diffusion regions which serve as resistor controlled from a common control voltage.
In still another embodiment of the invention, each diffusion region is surrounded by a single trench structure which controls the diffusion region.